Isolated temperature sensor device package

ABSTRACT

In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

This application is a continuation to patent application Ser. No.17/219,830, filed Mar. 31, 2021, the contents of all of which are hereinincorporated by reference in its entirety.

TECHNICAL FIELD

This relates generally to packaging semiconductor temperature sensordevices, and more particularly to packaging for semiconductortemperature sensors including electrical isolation.

BACKGROUND

For semiconductor temperature sensors, a semiconductor device includescomponents with a parameter that varies with temperature which can beused to develop a signal that varies predictably with temperature. Thecircuit is a temperature sensor. Semiconductor temperature sensors canuse an impedance, capacitance, inductance or a transistor voltagethreshold as a temperature sensor device, and circuitry can beimplemented to output a signal, a current or voltage, that depends onthe temperature sensor device and which varies with temperature. In anexample a capacitance is used which has permittivity that varies withtemperature. In another example, an impedance or pairs of impedances canbe used with a current source in a proportional-to-absolute-temperature(“PTAT”) circuit. Delta-VBE temperature sensing using bipolartransistors with changes in a base-to-emitter voltage characteristicover temperature can be used.

When sensing temperature for high voltage applications, thesemiconductor temperature sensor is exposed to the high voltage.Increasingly integrated devices are used for delivering increasingvoltages, for example hundreds or thousands of volts, to a load. Thearea of a system where a temperature sensor is needed, for example a busor a large conductor, may also have a high voltage on it. Thesemiconductor temperature sensor may not be capable of withstanding theelectric field associated with the high voltage. Failures in thesemiconductor temperature sensor can occur due to the dielectricbreakdown voltage of the semiconductor device. Electrical isolation isneeded for the temperature sensor device, even while the temperaturesensor is thermally coupled to the conductor or bus, or other surface ofinterest. Optical sensors are sometimes used to achieve the electricisolation, however not all applications provide a signal that isappropriate for optical sensing. Improvements in semiconductortemperature sensors are needed.

SUMMARY

In an example an apparatus includes: a package substrate having a diepad configured for mounting a semiconductor die, a first lead connectedto the die pad, and a second lead spaced from and electrically isolatedfrom the die pad; a spacer dielectric mounted on the die pad; asemiconductor die including a temperature sensor mounted on the spacerdielectric; electrical connections coupling the semiconductor die to thesecond lead; and mold compound covering the semiconductor die, the diepad, the electrical connections, and a portion of the package substrate,with portions of the first lead and portions of the second lead exposedfrom the mold compound to form terminals for a packaged temperaturesensor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a projection view of a small outline integrated circuit (SOIC)semiconductor device package.

FIG. 2 is a projection view of a quad flat no-lead (QFN) semiconductordevice package.

FIG. 3A is a projection view of a semiconductor wafer includingsemiconductor dies, FIG. 3B is a projection view of a semiconductor die.

FIG. 4 illustrates, in a projection view, a semiconductor device packageof an arrangement for a temperature sensor.

FIGS. 5A-5E illustrate in cross sectional views selected steps informing a packaged temperature sensor in an arrangement.

FIG. 6 illustrates in a projection view a packaged temperature sensor ofthe arrangement coupled to a bus.

FIGS. 7A-7B are graphs that illustrate electric field strengthsimulation results for example arrangements.

FIG. 8 illustrates, in a cross section, another arrangement for apackaged temperature sensor in a QFN package.

FIG. 9 illustrates in a flow diagram a method for forming a packagedtemperature sensor device of the arrangements.

DETAILED DESCRIPTION

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts, unless otherwise indicated. The figuresare not necessarily drawn to scale.

Elements are described herein as “coupled.” As used herein, the term“coupled” includes elements that are directly connected, and elementsthat are electrically connected even with intervening elements or wiresare coupled.

The term “semiconductor die” is used herein. As used herein, asemiconductor die can be a discrete semiconductor device such as abipolar transistor, a few discrete devices such as a pair of power FETswitches fabricated together on a single semiconductor die, or asemiconductor die can be an integrated circuit with multiplesemiconductor devices such as the multiple capacitors in an A/Dconverter. The semiconductor die can include passive devices such asresistors, inductors, filters, or can include active devices such astransistors. The semiconductor die can be an integrated circuit withhundreds or thousands of transistors coupled to form a functionalcircuit, for example a microprocessor or memory device. Thesemiconductor die can be a passive device such as a sensor, examplesensors include photocells, transducers, and charge coupled devices(CCDs). The semiconductor device can be a micro electro-mechanicalsystem (MEMS) device, such as a digital micromirror device (DMD).Semiconductor dies for power applications include a discrete powertransistor, a gate driver to operate the power transistor, passives suchas capacitors, inductors, and resistors needed to implement powercircuitry, and intelligent power devices that include protective sensorssuch as inrush current sensors that add reliability and control to thesystem. In some applications, these devices may be fabricated ofdifferent semiconductor materials, and can be separate semiconductordies that are mounted in a single device package. In the arrangements, asemiconductor die includes a temperature sensor.

The term “packaged electronic device” is used herein. A packagedelectronic device has at least one semiconductor die electronicallycoupled to terminals and has a package body that protects and covers thesemiconductor die. In some arrangements, multiple semiconductor dies canbe packaged together. For example, a power metal oxide semiconductor(MOS) field effect transistor (FET) semiconductor die and a secondsemiconductor die (such as a gate driver die or controller device die)can be packaged together to from a single packaged electronic device.Additional components such as passives can be included in the packagedelectronic device. The semiconductor die is mounted to a packagesubstrate that provides conductive leads, a portion of the conductiveleads form the terminals for the packaged electronic device. Thesemiconductor die can be mounted to the package substrate with an activedevice surface facing away from the package substrate and a backsidesurface facing and mounted to the substrate. Alternatively, thesemiconductor die can be flip-chip mounted with the active surfacefacing the substrate surface, and the semiconductor die is mounted tothe leads of the substrate by conductive columns or solder balls. Thepackaged electronic device can have a package body formed by a thermosetepoxy resin in a molding process, or by the use of epoxies, plastics, orresins that are liquid at room temperature and are subsequently cured.The package body may provide a hermetic package for the packagedelectronic device. The package body may be formed in a mold using anencapsulation process, however, a portion of the leads of the substrateare not covered during encapsulation, these exposed lead portionsprovide the exposed terminals for the packaged electronic device.

The term “package substrate” is used herein. A package substrate is asubstrate arranged to receive a semiconductor die and to support thesemiconductor die in a completed semiconductor package. Packagesubstrates include conductive lead frames, which can be formed fromcopper, aluminum, stainless steel and alloys such as Alloy 42 and copperalloys. The lead frames can include a die pad for mounting thesemiconductor die, and conductive leads arranged proximate to the diepad for coupling to bond pads on the semiconductor die using wire bonds,ribbon bonds, or other conductors. The lead frames can be provided instrips or arrays. Dies can be placed on the strips or arrays, the diesplaced on a die pad for each packaged device, and die attach or dieadhesive can be used to mount the dies to the lead frame die pads. Wirebonds can couple bond pads on the semiconductor dies to the leads of thelead frames. After the wire bonds are in place, a portion of thesubstrate, the die, and at least a portion of the die pad can be coveredwith a protective material such as a mold compound.

Alternative package substrates include pre-molded lead frames (PMLF) andmolded interconnect substrates (MIS) for receiving semiconductor dies.These substrates can include dielectrics such as liquid crystal polymer(LCP) or mold compound and can include one or more layers of conductiveportions in the dielectrics. The lead frames can include plated, stampedand partially etched lead frames, in a partially etched lead frame, twolevels of metal can be formed by etching a pattern from one side of themetal lead frame, and then from the other side, to form full thicknessand partial thickness portions, and in some areas, all of the metal canbe etched to form openings through the partial etch lead frames.Repeated plating and patterning can form multiple layers of conductorsspaced by dielectrics, and conductive vias connecting the conductorlayers through the dielectrics, the dielectrics can be mold compound.The package substrate can also be tape-based and film-based substratescarrying conductors; ceramic substrates, laminate substrates withmultiple layers of conductors and insulator layers; and printed circuitboard substrates of ceramic, fiberglass or resin, or glass reinforcedepoxy substrates such as FR4.

The term “quad flat no-lead” or “QFN” is used herein for a devicepackage. A QFN package has leads that are coextensive with the sides ofa molded package body and the leads are on four sides. Alternative flatno-lead packages may have leads on two sides or on one side. These canbe referred to as “small outline no-lead” or “SON” packages. No leadpackaged electronic devices can be surface mounted to a board. Leadedpackages can be used with the arrangements where the leads extend awayfrom the package body and are shaped to form a portion for soldering toa board. A dual in line package, or “DIP”, can be used with thearrangements. A thin DIP package arranged with leads for surfacemounting can be referred to as a small outline integrated circuit or“SOIL” package.

The term “high voltage” is used herein. As used herein a “high voltage”is a voltage greater than 50 Volts. The arrangements can be used insystems where hundreds or thousands of volts are being delivered to aload. In an example, a 4 kVrms signal was used. Further, even inexamples where average voltage is less than these levels, transientsmust be considered that much greater. In an example where a 300 Vrmslevel is expected on a signal or buss, a transient voltage of 2500 Vrmsmust be handled, since when a signal switches from off to on, or viceversa, a transient of that level can occur. Voltage isolation betweenisolated elements must be able to handle both the expected loadvoltages, and transients that can occur.

The term “spacer dielectric” is used herein. A spacer dielectric as usedherein is a dielectric material that has a thermal conductivity ofgreater than 10 Watts per meter-Kelvin (W/mK). Some spacer dielectricsuseful in the arrangements are ceramics, composites, or glasses.

In the arrangements, a semiconductor die including a temperature sensoris thermally coupled to an input and is provided in a semiconductordevice package where the semiconductor die is electrically isolated froman input, which may be at a high voltage, by use of a thermallyconductive spacer dielectric within the package. A die pad of a packagesubstrate is coupled to a first input or group of inputs that may beused to sense temperature at a signal or surface. A spacer dielectric ofa sufficient thickness to provide electrical isolation is mounted to thedie pad. A semiconductor die including a temperature sensor is mountedto the spacer dielectric and is thermally coupled to the die pad. Byarranging the spacer dielectric to be of sufficient thickness, thetemperature sensor can be thermally coupled to a signal or surface forsensing the temperature, while the semiconductor die is electricallyisolated from the surface or signal. Even in a case where a surfacebeing sensed is at a high voltage, the semiconductor die is isolatedfrom the electric field in the package due that can occur due to thehigh voltage. Additional input and output signals that are alsoelectrically isolated from the die pad can be used to provide controland data signals for the temperature sensor. Temperatures that can beexpected for semiconductor devices in power applications can exceed 250degrees C., for example over 300 degrees C. Temperature sensors areoften applied at portions of systems where these high temperatures mayoccur, to enable shutting down components when an over temperaturecondition is detected, for example.

FIG. 1 illustrates in a projection view a DIP package that is usefulwith certain arrangements. The DIP package can be a small outlineintegrated circuit (SOIC) package which is thinner and takes less spaceon an system board than other DIP packages. In FIG. 1 , device package101 has eight leads extending from a body formed by use of a moldcompound. Mold compounds used in semiconductor packaging can be usedwith the arrangements, for example thermoset epoxy resin mold compoundcan be used to cover the semiconductor die, portions of a packagesubstrate such as a lead frame, and portions of the leads.

FIG. 2 illustrates, in another projection view, a board side surface ofa QFN package useful with the arrangements. In FIG. 2 , the QFN package201 has a body formed from mold compound, and a die pad with an exposedsurface, as well as terminals near the die pad for coupling to a signalbus, conductor, trace or surface to be sensed, and terminals space fromthe die pad that are electrically isolated from the die pad. The QFNpackage 201 can be surface mounted to a system board using solder andsurface mount technology (SMT), QFN packages are increasingly usedbecause the non-leaded package bodies require less board area thanleaded packages, such as the DIP 101 in FIG. 1 . The semiconductor diecan be packaged in a DIP device package, an SOIC device package, in aQFN package, or in another semiconductor package type. Packages withleads or no-leads packages can be used with the arrangements. DIP, SOIC,QFN packages, small outline packages (SOP), small outline no-lead (SON)packages, and quad flat package (QFP) packages, as well as otherpackages for semiconductor devices, can be used with the arrangements.

FIGS. 3A and 3B illustrate a semiconductor wafer including a pluralityof semiconductor dies and a single semiconductor die after it has beenremoved from the semiconductor wafer in a singulation process,respectively. In FIG. 3A, a semiconductor wafer 338 is shown with aplurality of semiconductor dies 310 arranged in rows and columns andspaced by scribe lines 342, shown in a vertical direction as thesemiconductor wafer 338 is oriented in FIG. 3A, and 340 , shown in ahorizontal direction in FIG. 3A. After semiconductor dies including atemperature sensor are manufactured using semiconductor fabricationprocesses, the wafer is singulated into unit dies by the use of a saw orlaser cutting tool to cut the dies 310 apart from the wafer 338 alongthe scribe lines 340 and 342. FIG. 3B illustrates a single rectangularsemiconductor die such as can be used in the arrangements. A temperaturesensor circuit can be formed on the semiconductor die 310 using any oneof several types of sensor circuits and including at least one componentthat has a characteristic which varies predictably with devicetemperature.

FIG. 4 illustrates in a projection an example arrangement 401 using aSOIC DIP package to package a temperature sensor. In FIG. 4 , asemiconductor die 310 is shown mounted on a package substrate 403. Inthe illustrated example of FIG. 4 the package substrate is a metal leadframe, such as a copper lead frame. Other conductive lead framematerials can be used, such as stainless steel and Alloy 42. Partiallyetched or half etched lead frames can be used. PMLF substrates,including conductors spaced by dielectric material such as moldcompound, MIS substrates, and other substrates used in semiconductorpackaging can be used.

Package substrate 403 includes a die pad 409, and a first lead or groupof leads 411 coupled to the die pad 409. The leads 411 shown at one sideof the arrangement 401 may be an input for the device and may beattached to a surface or conductor where the temperature is to besensed, such as a bus trace on a system board. Package substrate 403also includes a second group of leads 405 of package substrate 403 isshown at a side opposite the first group of leads. The second group ofleads 405 is electrically isolated from the die pad 409 and the firstgroup of leads 411, and as is described below, a lead or leads 405 canbe electrically connected to the semiconductor die 310, by bond wiresfor example, to use in communication with external devices.

A spacer dielectric 413 is shown mounted on die pad 409. The spacerdielectric can be one of several dielectric materials that are thermalconductors and electric isolators, and can be a ceramic material.Examples that are useful in the arrangements include aluminum nitride(AlN), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), hafnium oxide(HfO₂), barium titanium oxide (BTO), molybdenum disulfide (MoS), siliconcarbide (SiC), glasses, and composites made of multiple materials. Thespacer dielectric 413 can have varying thicknesses with a particularthickness determined by the properties of the material, and by the needsof a particular application. The spacer dielectric in the arrangementswill have a thermal conductivity of greater than or equal to 10 W/mK.The spacer dielectric in the arrangements is an electrical insulator. Byusing the spacer dielectric in a package to thermally couple thesemiconductor die to the pad and also a lead, and by electricallyisolating the semiconductor die from the die pad, the semiconductor dieis protected from the electric field due to the high voltage on the diepad. In one example, a spacer dielectric of AlN was used at a thicknessof 125 microns, and in another example, AlN was used at thickness of 250microns. AlN has a thermal conductivity of 160 W/mK at 25 degrees C. Asis further detailed below, in both examples simulations show that theelectric field in the semiconductor die is less than 10 Volts/micron,with a 4 kVrms voltage input at the input leads 411. Spacer dielectric413 may have planar surfaces, or may have a cup shaped recess forreceiving the semiconductor die 310 in a surface, as is furtherdescribed below. A die attach material 415 is used to attach thesemiconductor die 310 to the spacer dielectric 413, which can be aconductive die attach, a non-conductive die attach, or a non-conductivedie attach film. Another die attach is also used to attach spacerdielectric 413 to die pad 409 (not visible in FIG. 4 ) which can be thesame die attach material or another die attach material. Die attachepoxies or die attach films, both conductive and non-conductive types,can be used to form arrangements. Mold compound 417 forms the packagebody and covers the semiconductor die 310, the die pad 409, and portionsof leads 405 and 411, while other portions extend from the mold compoundto form terminals for the packaged semiconductor device of arrangement401. Use of the spacer dielectric with high thermal conductivity andhigh electrical isolation results in a temperature sensor in thesemiconductor device 310 that is electrically isolated from leads 411,which are configured to be mounted to a high voltage area wheretemperature is to be measured, while being thermally coupled to theleads 411.

FIGS. 5A-5E illustrate, in a series of cross sectional views, a methodfor forming an arrangement. In FIG. 5A, the package substrate 403, whichin this example is a metal lead frame, has leads 411 coupled to the diepad 409, which is configured for mounting devices. Although severalleads 411 are shown in FIG. 4 , in another example arrangement, one leador many leads 411 can be used. Using multiple leads in parallel to acommon signal reduces resistance and may improve performance in someapplications. Leads 405 are spaced from the die pad 409 and will beelectrically isolated from the die pad 409 and the leads 405.

FIG. 5B illustrates, in another cross section, the arrangement of FIG.5A after additional processing. In FIG. 5B, spacer dielectric 413 isshown mounted to die pad 409. Die attach 412 is used to mount the spacerdielectric 413. The die attach material can be a conductive die attach.The die attach material can be a non-conductive die attach, however,because in the presence of a high voltage at the input (leads 411) anyvoids in a non-conductive die attach can cause a concentration in anelectric field between the die pad 409 and the spacer dielectric 413,the non-conductive die attach should be void free to avoid concentratedelectric fields that might occur in voids of non-conductive die attach.A non-conductive die attach film (NCDAF) may be used to form a void freenon-conductive die attach layer. Spacer dielectric 413 can be of one ofseveral insulators that are thermally conductive and are good electricisolators. Aluminum nitride (AlN) is one example of a ceramic that isuseful in the arrangements. The thickness of the spacer dielectric 413can vary, from about 50 ums to several hundred microns. In particularexamples, a thickness of 125 microns was evaluated and a thickness of250 microns was evaluated using AlN ceramic in an SOIC package with 8terminals. A stress volume characteristic Sv/t observed for packagesusing spacer dielectrics at these thicknesses were similar to moldcompound, and so these materials are appropriate for packageapplications. AlN has little change in permittivity over a broadtemperature range, and has low electrical conductivity over a range oftemperatures, including temperatures greater than 200 degrees C. Othermaterials with similar characteristics can be used, including otherceramics such as aluminum oxide (Al₂O₃), titanium oxide (TiO₂), hafniumoxide (HfO₂), and barium titanium oxide (BTO), molybdenum disulfide(MoS), silicon carbide (SiC), glass, and composites made of multiplelayers of these materials or including these materials.

FIG. 5C illustrates, in another cross section, the structure of FIG. 5Bafter further processing. In FIG. 5C, semiconductor die 310 is mountedto the spacer dielectric 413 using a second die attach 415. The seconddie attach 415 can be the same material as die attach 412 or can be ofdifferent die attach material. Conductive die attach can be used.Non-conductive die attach film can be used, as described above.Semiconductor die 310 includes a component or components that areconfigured as temperature sensors. Semiconductor die is thermallycoupled to die pad 409 and leads 411, but is electrically isolated fromboth. Because the spacer dielectric 413 provides electrical isolation,the semiconductor die 310 experiences a lower electric field even whenhigh voltages are applied to leads 411, at the input to the package ofthe example arrangement.

In FIG. 5C, the spacer dielectric 413 is shown having planar exteriorsurfaces for mounting to the die pad (the lower surface of spacerdielectric 413, as oriented in FIG. 5C) and for mounting thesemiconductor die 310 (the upper surface of spacer dielectric 413 asoriented in FIG. 5C). In an alternative arrangement (not shown), spacerdielectric 413 can have a recessed upper surface to form a cup shape forreceiving the semiconductor die 310, which can add additional isolationfor the semiconductor die 310 by covering the sides of the semiconductordie 310.

FIG. 5D illustrates, in another cross section, the structure of FIG. 5Cafter additional processing. In FIG. 5D, bond wires 417 are used tocouple the semiconductor die to the leads 405. Leads 405 areelectrically isolated from the die pad 409 and leads 411. Leads 405 canbe coupled to input and output signals to allow for communicationbetween semiconductor die 310 and an external device. Signals needed forthe semiconductor die 310 to operate, including power, ground and clocksignals, can be provided at leads 405.

FIG. 5E illustrates in another cross section, the packaged device 401after an encapsulation molding process is performed on the structure ofFIG. 5D. Mold compound 419 can be applied by a molding process such as atransfer molding process using a thermoset epoxy resin mold compound.Thermoset mold compound can be provided as a solid puck or powder,heated to liquefy the mold compound, and allowed to flow into a mold tocover the die pad, the semiconductor die, the spacer dielectric, thebond wires, the die attach, and portions of the leads 405 and 411 ofpackage substrate 403. The mold compound cures to form a solid packagebody 419. Portions of leads 405, 411 are left exposed from the moldcompound 419 to form leads for mounting the device to a printed circuitboard. Other materials can be used such as resins, epoxies, and plasticto cover the devices and form the body of the package.

FIG. 6 illustrates in an example application the packaged temperaturesensor device package 401 coupled to a bus 610 to sense temperature ofthe bus 610. The leads 411 couple the bus 610 to the device 401, withdie pad 409 inside the packaged device thermally and electricallycoupled to the bus 610. The semiconductor die 310 is thermally coupledto the bus 610, but is electrically isolated from it by spacerdielectric 413.

FIG. 7A illustrates in a graph the electric field observed insimulations within the packaged device 401 when a 4 kVrms signal isapplied to the leads 411 using an AlN spacer of 250 microns thickness.As seen in FIG. 7A, the darker areas have lower electric field Ev, whilelighter areas indicate larger electric fields. The maximum electricfield observed was 22 V/um within the spacer dielectric of AlN. Thefield in the semiconductor device 310 was much lower, as indicated bythe dark shading, and was less than 10 V/um.

FIG. 7B illustrates in another graph the electric field observed withinthe packaged device 401 when a 4 kVrms signal is applied to the leads411 using an AlN spacer of 125 microns thickness. As seen in FIG. 7B,the darker areas have lower electric field, while lighter areas indicatelarger electric fields. The maximum electric field observed was 44 V/umin the spacer dielectric of 125 microns of AlN. The field in thesemiconductor device 310 was much lower in this example as well, andagain was less than 10 V/um.

FIG. 8 illustrates in an alternative arrangement a packaged device 801in a QFN package. Mold compound 419 covers a semiconductor die 310including a temperature sensor, which is attached to a spacer dielectric413 by a die attach layer 415. A second die attach 412 is used to attachthe spacer dielectric 413 to the die pad 809 of a package substrate 803,which can be a metal lead frame. Leads 811 are physically attached andelectrically coupled to the die pad and provide a thermal connection tothe die pad from an input of the packaged device 801. Leads 805 areelectrically isolated from the die pad 809 and leads 811, and areconnected to the semiconductor die 310 by bond wires. Ribbon bonds oranother electrical connection can be used to couple leads 805 to thesemiconductor die 310. The mold compound covers portions of the packagesubstrate 803 but leaves portions of leads 805, die pad 809 and leads811 exposed to make thermal and electrical connections to the packageddevice 801.

FIG. 8 illustrates an overhang distance D1 used in the arrangements. Thespacer dielectric 413 has an overhang extending past the edge of thesemiconductor die 310 by a distance of at least 10 mils, or 0.254 mm.This overhang ensures a minimum creepage distance is maintained betweenthe die pad (809 in FIG. 8 ) and the die 310, to prevent unwantedelectric coupling such as an arc from the die pad to the semiconductordie when a high voltage is present. By having the spacer dielectric witha greater width on all sides than the die, so that it overhangs the dieon all four sides, the creepage distance is increased, preventing arcingbetween the die pad and the semiconductor die.

In alternative arrangements, the spacer dielectric can have metal plateson the planar surfaces where the die attach is shown, and when metalplates are present on the spacer dielectric, solder can be used toattach the die 310 to the spacer dielectric 413, and to attach thespacer dielectric 413 to the die pad 809 of the metal lead frame. Themetal plates should also be spaced from the edge of the spacerdielectric and be of similar size as the die 310, so that the creepagedistance between the die pad 809 or 309 and the die 310 is maintained.

FIG. 9 illustrates, in a flow diagram, a method for forming anarrangement. In step 901, a spacer dielectric is mounted to a die pad ofa package substrate, and the package substrate has at least one firstlead connected to the die pad (see FIG. 5B, spacer dielectric 413 ismounted on die pad 409 of package substrate 403, with lead 411 attachedto the die pad 409.). At step 903, the method continues by mounting asemiconductor die including a temperature sensor to the spacerdielectric (see FIG. 5C, semiconductor die 310 is mounted to spacerdielectric 413). The spacer dielectric provides a thermal couplingbetween the semiconductor die and the die pad, which is also thermallycoupled to the first lead. The semiconductor die is electricallyisolated from the die pad by the spacer dielectric. At step 905, themethod continues by electrically connecting a lead from a second set ofleads that are electrically isolated from the die pad to thesemiconductor die, the electrical connections can be formed by wirebonding, or by ribbon bonding (see FIG. 5D where bond wire 417 couplesthe second leads 405 to the semiconductor die 310). The second set ofleads are isolated from the die pad.

At step 907, the method completes by covering the semiconductor die, thedie pad, and portions of the first and second set of leads with moldcompound to form a packaged temperature sensor device (see FIG. 5E,where mold compound 419 covers the elements). Encapsulation using athermoset resin epoxy mold compound can be used.

The packaged temperature sensor device can be used as shown in FIG. 6 bycoupling the lead or leads 411 to a bus or surface where temperature ismeasured. Alternative applications include mounting a QFN package suchas 801 shown in FIG. 8 with the exposed portion of the die pad inthermal contact with a surface or conductor on a board, module, ordevice where temperature is to be sensed. When a high voltage is presentat the surface to be sensed, the semiconductor die is electricallyisolated from the high voltage so that the temperature sensor is notdamaged due to dielectric breakdown in the presence of an electric fieldassociated with the high voltage.

Modifications are possible in the described arrangements, and otheralternative arrangements are possible within the scope of the claims.

What is claimed is:
 1. A semiconductor package comprising: a packagesubstrate having a die pad, a first lead connected to the die pad, and asecond lead electrically isolated from the die pad; a dielectriccomponent on the die pad; a semiconductor die including a temperaturesensor on the dielectric component; electrical connections coupling thesemiconductor die to the second lead; and mold compound covering thesemiconductor die, the die pad, the electrical connections, and aportion of the package substrate, with portions of the first lead andportions of the second lead exposed from the mold compound to formterminals of the semiconductor package.
 2. The semiconductor package ofclaim 1, wherein the dielectric component comprises aluminum nitride. 3.The semiconductor package of claim 1, wherein the dielectric componentis one selected from: aluminum nitride (AlN), aluminum oxide (Al₂O₃),titanium oxide (TiO₂), hafnium oxide (HfO₂), and barium titanium oxide(BTO), molybdenum disulfide (MoS), silicon carbide (SiC), composites ofthese, and glass.
 4. The semiconductor package of claim 1 wherein thedielectric component has a thermal conductivity of greater than 10 W/mK.5. The semiconductor package of claim 1, wherein the dielectriccomponent has a thickness of between 50 microns and 500 microns.
 6. Thesemiconductor package of claim 1, wherein the dielectric component has athickness selected from 125 microns and 250 microns.
 7. Thesemiconductor package of claim 6, wherein the dielectric component isAN.
 8. The semiconductor package of claim 1, wherein the semiconductordie is mounted in a recess in a surface of the dielectric component. 9.The semiconductor package of claim 1, wherein the electrical connectionsfurther comprise bond wires.
 10. The semiconductor package of claim 1,wherein the dielectric component is mounted to the die pad by aconductive die attach.
 11. The semiconductor package of claim 1, whereinthe dielectric component is mounted to the die pad by a non-conductivedie attach film.
 12. The semiconductor package of claim 1, wherein thesemiconductor die is mounted to the dielectric component by a conductivedie attach.
 13. The semiconductor package of claim 1, wherein thesemiconductor die is mounted to the dielectric component by anon-conductive die attach film.
 14. The semiconductor package of claim1, wherein the dielectric component has metal platings on a firstsurface and on a second opposite surface, and the dielectric componentis mounted to the die pad by solder between the first surface and thedie pad, and the semiconductor die is mounted to the second surface ofthe dielectric component by solder.
 15. The semiconductor package ofclaim 1, wherein the package substrate is one of a lead frame, apartially etched lead frame, a pre-molded lead frame (PMLF), a moldedinterconnect substrate (MIS), and a printed circuit board.
 16. Apackaged temperature sensor device, comprising: a first lead to sense atemperature of a conductive element; a die pad of a metal lead framethat is connected to the first lead; a spacer dielectric attached to thedie pad; a semiconductor die attached to the spacer dielectric; a secondlead of spaced from the die pad and the first lead, and electricallyisolated from the die pad; bond wires connecting the second lead to thesemiconductor die; and mold compound covering the semiconductor die, thedie pad, the spacer dielectric, and portions of the first lead and thesecond lead, while additional portions of the first lead and the secondlead are exposed from the mold compound, forming terminals for thepackaged temperature sensor device, wherein a cross-sectional length ofthe spacer dielectric is more than a cross-sectional length of thesemiconductor die.
 17. The packaged temperature sensor device of claim16 wherein the spacer dielectric has a thermal conductivity that isgreater than 10 W/mK.
 18. The packaged temperature sensor device ofclaim 16, wherein the spacer dielectric is one selected from aluminumnitride (AlN), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), hafniumoxide (HfO₂), and barium titanium oxide (BTO) molybdenum disulfide(MoS), silicon carbide (SiC), composites of these, and glass.
 19. Thepackaged temperature sensor device of claim 16, wherein the spacerdielectric has a thickness between 50 microns and 500 microns.
 20. Thepackaged temperature sensor device of claim 16, wherein spacerdielectric is attached to the die attach pad via a die attach material,and wherein a cross-sectional length of the die attach material is morethan the cross-sectional length of the die and less than thecross-sectional length of the dielectric spacer.